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| AND711AST-30/-EO 240 x 64 Dots Intelligent Graphic Display The AND711AST-30/-EO is a full dot matrix LCD module including an LCD controller and display RAM. This device can display graphic patterns and symbols and is suitable for a message display for various instruments such as business machine terminals. Features * * * * * * * * * * * * RoHS Compliant Absolute Maximum Ratings Item Supply Voltage EL Drive Voltage (fEL = 1 kHz) Input Voltage Operating Temperature Storage Temperature EL Driving Freq. (EO) Symbol VDD VEE VEL VIN Top Tstg fEL Rating 5.5 -19 130 -.3 VIN +.3 0 to +50 -20 to +70 1 Unit V Vrms V C C kHz Super twist 40 character x 8 line capability Excellent readability and high contrast ratio 8-bit parallel bus for read/write data by CPU interface Built-in LCD controller and display RAM (8k byte) Character mode, graphic mode, and character and graphic combination mode RoHS compliant Wide operating temperatures range (0C to + 50C) Compact and easily mounted on any equipment User-selectable font-6 x 8 or 8 x 8 Available with EL backlighting attached (-EO option) Dot Matrix Dimensions Electrical Characteristics (TA = 25C) Item Supply Voltage High Level In Voltage (VDD = 5.0V) Low Level In Voltage (VDD = 5.0V) Mechanical Characteristics Item Outline Dimensions Number of Dots # of Characters Viewing Area Bezel Opening Dot Size Dot Pitch Weight (approx.) Specification 180 (W) x 65 (H) x 10 (D) 240 (W) x 64 (H) 40 x 8 (320) Characters 6 x 8 dot format, alpha-numeric 132 (W) x 39 (H) 132 (W) x 39 (H) 0.49 (W) x 0.49 (H) 0.53 (W) x 0.53 (H) I20/150 (ST/EO) mm mm mm mm gram Product specifications contained herein may be changed without prior notice. It is therefore advisable to contact Purdy Electronics before proceeding with the design of equipment incorporating this product. 7/20/07 Symbol VDD VEE VIN VIL VOH VOL IDD Min. 4.5 -5.75 2.8 - VDD -0.3 - - - - Typ. 5.0 -8.5 - - - - 16.0 2.4 4.0 Max. 5.5 -11.5 5 Unit V V 0.8 - 0.3 25.0 3.0 10 V V mA (2) Unit mm High Level Output Volt. (VDD = 5.0V) Low Level Output Volt. (VDD = 5.0V) Power Consumption(1) IEE IEL 1. All dots on. (V DD = .5V, V EE = -8.5V, V EL=110, fEL = 500 Hz or at Typ.) 2. mA rms 1 Purdy Electronics Corporation * 720 Palomar Avenue * Sunnyvale, CA 94085 Tel: 408.523.8200 * Fax: 408.733.1287 * sales@purdyelectronics.com * www.purdyelectronics.com AND711AST-30/-EO Intelligent Graphics Display Optical Characteristics (TA = 25C, = 0, = 0) Item Viewing Angle Contrast Turn On Turn Off Symbol Right to Left Up & Down K Ton Toff Min. - - 2.5 Typ. 80 55 4.8 200 250 Max. - - 350 300 Unit degree ms ms Temperature Variations Temperature 0C +25C +50C V DD -V EE Power Supply The LCD panel is driven by the voltage VDD -VEE, so an adjustable VEE is required for contrast control and temperature compensation. 13.9 12.5 10.8 Note: Refer to Applications Section for definitions of viewing angle, contrast ratio, response time (on and off) and luminance. Connector Pin Assignment Pin No. 1 2 3 4 5 6 7 Signal FGND GND VDD VEE WR RD CE Function Frame Ground (connected to metal bezel) Ground (signal) Power Supply for logic (5V) Power Supply for LCD Drive (-8.5 3V) Data Write Data Read Chip Enable WR = "L", C/D = "H": Command Write WR = "L", C/D = "L": Data Write RD = "L", C/D = "H": Status Read RD = "L", C/D = "L": Data Read No connection Controller Reset (Active Pullup Required) Data Input/Output Data Input/Output Data Input/Output Data Input/Output Data Input/Output Data Input/Output Data Input/Output Data Input/Output Font select. Open or connect to VDD : 6 x 8 dot Connect to ground: 8 x 8 dot No connection C/D R2 Example of Variable Negative Voltage Supply V DD GND R1 TR V EE LCD Module R1 = 10k, R2 = 10k, TR 2SA1102 or equivalent Timing Relationships and Diagram Signal Timing Relationships Item C/D Set Up Time C/D Hold Time CE , RD, WR 8 C/D Symbol tCDS tCDH tCE, tRD, tWR tDS tDH tACC tOH Min. 100 10 80 80 40 - 10 Max. - - - - - 150 50 Unit 9 10 11 12 13 14 15 16 17 18 19 20 NC RESET D0 D1 D2 D3 D4 D5 D6 D7 FS NC Pulse Width Data Set Up Time Data Hold Time Access Time Output Hold Time Timing Diagram ns tCDS CE tCP,tRD,tWP RD, WR tDS D0-D7 (WRITE) D0-D7 (READ) tACC tCDH tDH tOH 7/20/07 Purdy Electronics Corporation * 720 Palomar Avenue * Sunnyvale, CA 94085 Tel: 408.523.8200 * Fax: 408.733.1287 * sales@purdyelectronics.com * www.purdyelectronics.com 2 AND711AST-30/-EO Intelligent Graphics Display Block Diagram Because signal lines are directly connected to C-MOS and are not pull-up or pull-down internally, except RESET which is pull-up to VDD, you must guard all signals from external noise. 8 D0-D7 WR RD CE C/D RESET HSCP FR LP CDATA T6963C D0-D7 13 AD0-AD12 R/W CE ED I/O0-I/O7 A0-A12 RAM (8K byte) X-Driver X-Driver X-Driver Control Lines 80 80 80 64 Y-Driver LCD Panel 240 x 64 Dots VEL VEL EL Backlight Dimensional Outline 3 Purdy Electronics Corporation * 720 Palomar Avenue * Sunnyvale, CA 94085 Tel: 408.523.8200 * Fax: 408.733.1287 * sales@purdyelectronics.com * www.purdyelectronics.com 7/20/07 |
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